This invention relates generally to the semiconductor feature known as via holes, or xe2x80x9cvias,xe2x80x9d and more particularly to routing channels among such vias.
Via holes, or more simply xe2x80x9cvias,xe2x80x9d are semiconductor device features that are through holes made in a substrate, for a variety of different purposes. Via holes may be used to ground semiconductor devices and passive devices. Via holes may be made through dielectric layers, for subsequent metal deposition to form a plug and create an interconnect between two metal lines. Multi-level interconnect schemes may employ such via holes. Processes used to perform such interconnection using via holes include the damascene process and the dual-damascene process, among other processes.
Within an integrated circuit (IC) layout that has a number of metal layers, vias are particularly employed to connect signals from lower metal layers to upper metal layers. However, the presence of the vias blocks the routing of wires horizontally. The typical solution to this difficulty is to add a limited number of routing channels among the vias. Wires can then be placed or fabricated through or within the routing channels to enable horizontal routing along one or both axes of the horizontal plane. Thus, using routing channels enables horizontal routing through the IC layout.
A difficulty with this current deployment of routing channels, however, is that they do not provide flexible routing within the IC layout. In particular, the placement orientation of the layout relative to the horizontal plane may have to be fixed, so that the wires running through or within the routing channels remain in the same direction relative to the routing channels. This constrains semiconductor designs and fabricators in designing and fabricating semiconductor IC""s. In turn, this adds cost to the semiconductor device design and fabrication processes, as well as introducing delay into these oftentimes-critical processes.
FIG. 1 shows an exploded three-dimensional perspective view of a sample IC layout 100 that exhibits the routing inflexibility of placing routing channels among vias in the prior art. Three layers of the IC layout 100 are shown: top and bottom inter-metal dielectric (IMD) layers 102 and 106, sandwiching a middle metal layer 104. Via holes are located within the IMD layers 102 and 106, to connect the middle metal layer 104 with other metal layers above and below the middle metal layer 104, respectively. However, they are not shown in FIG. 1 for illustrative clarity.
A horizontal plane is defined by the x-axis 112 and the y-axis 114. Thus, whereas the via holes not shown in FIG. 1 connect the metal layer 104 to other metal layers through the IMD layers 102 and 106 along the z-axis 116, the routing channels enable routing wire, such as copper or aluminum wire, to route through the IC layout 100 along the horizontal plane. In particular, there are two routing channels through the metal layer 104 represented by the arrows 108, along the x-axis 112. However, there are no corresponding routing channels through the metal layer 104 along the y-axis 114, as aptly indicated in FIG. 1 by the blocked arrow 110.
This means that once the orientation of the semiconductor device represented by the IC layout 100 of FIG. 1 is determined relative to the routing wires through the IC layout 100, the orientation cannot be subsequently changed. For example, the positioning of the IC layout 100 cannot be rotated ninety degrees. This is because the routing wires that pass freely through the routing channels represented by the arrows 108 along the x-axis 112 cannot pass freely along the y-axis 114. Thus, the semiconductor designers and fabricators are restricted to the initially determined orientation.
Therefore, there is a need for improved flexibility in positioning semiconductor IC layouts relative to routing wires passing through routing channels among vias. Such improved flexibility should desirably ensure that the orientation of IC layouts relative to their routing wires can be rotated as necessary by semiconductor designers and fabricators. That is, the orientation of IC layouts relative to their routing wires can be reconfigured even after initial determination. For these and other reasons, there is a need for the present invention.
The invention relates to flexible routing channels among vias. A semiconductor device of an embodiment of the invention includes a number of metal layers, a number of dielectric layers, a number of via holes, and a number of routing channels. The metal layers are organized along a vertical axis. The dielectric layers are alternatively positioned relative to the metal layers. The via holes are situated within the dielectric layers and electrically connect a lower layer of the metal layers to an upper layer of the metal layers. The routing channels are situated within the metal layers and provide for electrical routing through the device along at least one of two horizontal axes of a horizontal plane perpendicular to the vertical axis.
Embodiments of the invention provide for advantages over the prior art. The routing channels enable a semiconductor layout of the semiconductor device to be rotated during the design and/or fabrication thereof without affect the electrical routing of wires or other metal elements through the routing channels. Thus, the orientation of the layout can be rotated relative to the routing wires even after initial determination thereof. That is, the layout can be rotated as necessary be designers and/or fabricators of the layout and the semiconductor device. Other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.